1. Field of the Invention
The present invention relates to a phase-locked loop oscillator for generating an output clock signal synchronized to an input clock signal and substantially free from phase variations of the input clock, and also relates to a moving-average circuit, and a division-ratio equalization circuit, suitable for use in the same. More particularly, the invention relates to a phase-locked loop oscillator for generating, from a fixed-frequency oscillator output, an output clock signal synchronized to an input clock signal, and substantially free from phase variations of the input clock, by uniformly controlling a dual-modulus frequency divider that operates with a division ratio selected from two division ratios, and also relates to a moving-average circuit, and a division-ratio equalization circuit, suitable for use in the same.
2. Description of the Related Art
In synchronous multiplexing transmission systems such as SDH (synchronous digital hierarchy) and SONET (synchronous optical network) systems, a highly stable clock signal, that serves as a reference for network synchronization, is transmitted from a master station to a slave station, and further to the next slave station and so on. Each slave station receives the clock signal transmitted from the master station or from another slave station on the master station side, and generates a synchronized clock signal for transmission to the next slave station.
The phase-locked loop oscillator in each slave station must have phase lock characteristics that can suppress the jitter and wander contained in the clock signal input from the transmission channel and that allows a sufficiently stable clock signal to be transmitted to the next slave station. Generally, phase variations with a frequency greater than 10 Hz are defined as wander, and those with a frequency less than 10 Hz are defined as jitter.
In the case of synchronous networks provided by NTT (Nippon Telegram and Telephone Public Corp.), for example, since the networks are constructed so that synchronization is applied to a signal with a narrow bandwidth by using a high precision network synchronizing apparatus, narrow loop bandwidth phase-looked loop oscillators constructed from microprocessors are used.
On the other hand, since the clock is not always supplied from a high precision clock source in North America and other areas, it is required that while providing for a wide capture-frequency range, a highly stable output clock, that can meet the specifications, be supplied. Furthermore, since no special clock supply apparatus is incorporated, there is a need for a small-sized phase-locked loop oscillator that fits inside a transmitting apparatus.
The present inventors contemplate providing a phase-locked loop oscillator applicable to the latter system. More specifically, the phase-locked loop oscillator contemplated in the invention is aimed at satisfying the following requirements: capture-frequency range is.+-.20 ppm; short-term stability is 5.times.10.sup.-9, that is, the ratio of wander amplitude of output clock to wander amplitude of input clock is 5.times.10.sup.-9 or less; resistance to jitter is 1.5 UI, 10-150 Hz, that is, the phase variation of the output clock is held within the specified value when jitter with amplitude 1.5 times the clock cycle is input within the frequency range of 10 to 150 Hz; and compactness.
One of the present inventors has previously proposed, in U.S. patent application Ser. No. 08/189,462, a phase-locked loop oscillator that can satisfy the above requirements. According to the proposed phase-locked loop oscillator, in a first phase-locked loop, the phase of the output obtained by dividing a fixed-frequency oscillator output by a dual-modulus frequency divider with a division ratio of N or N+1 is compared with the phase of an input clock signal; at each comparison, if there is a phase lag, the division ratio is set to N (advance control in the first loop), and conversely, if there is a phase lead, the division ratio is set to N+1 (delay control in the first loop). The number of advance control events is counted over a predetermined period of time, and the moving average of the count values is taken. The moving average value for the number of advance control events in the first loop corresponds to the mean frequency of the input clock signal. This moving average value is used to calculate control values for advance control and delay control in a second loop. In the second phase-looked loop, the same fixed-oscillator output used in the first phase-locked loop is frequency-divided by a second dual-modulus frequency divider. The output of the divider is phase-compared with the input clock; if there is a lag, the control value for the advance control is selected, and if there is a lead, the control value for the delay control is selected. A control signal for controlling the second dual-modulus frequency divider is created from the selected control value, and the control signal is supplied to the frequency divider.
As described above, in the previously proposed phase-locked loop oscillator, the input clock and output clock are phase-compared; however, only phase lag or phase lead information is reflected in the control, and the amount of phase difference is not measured and, therefore, is not reflected in the control.
Further, for the moving-average circuit for calculating the mean frequency and mean phase difference, a possible configuration would be to connect a required number of latch circuits in series and add the values latched in the latch circuits using adders (no dividers are needed if the required number is 2.sup.n). In this configuration, however, if the number of latch circuit stages is increased, the number of adder circuits required will also increase. For example, if the number of latch circuit stages is n and the number of bits is 20, then a number, (n-1), of 20-bit parallel adders will have to be provided.
In Japanese Patent Examined Publication No. 57-169874, there is proposed a configuration in which input values are cumulatively added in an endless manner and an input value delayed through a shift register by a predetermined number of samples is subtracted from the cumulative value, thereby achieving a required number of additions using one adder and one subtractor.
This configuration, however, has the problem that if a cumulative value is changed due to noise or other effects, the change will continue to affect the subsequent operations.
Furthermore, in the dual-modulus frequency divider capable of selecting one division ratio from two division ratios, since the control value is given in the form of a fraction with the denominator constant, that is, as the number of times one division ratio should be selected in the predetermined number of control events, a division-ratio equalization circuit needs to be provided which, based on the control value, performs control for the division ratio to be distributed at equally spaced intervals along the time axis so that the dual-modulus frequency divider outputs a clock signal free from jitter and wander.